?2014. renesas electronics cor poration, all rights reserved. page 1 of 9 renesas technical update 1753, shimonumabe, nakahara-ku, kawa saki-shi, kanagawa 211-8668 japan renesas electronics corporation renesas technical up date tn-rx*-a000a/e date: feb . 25 , 2014 this document describes disclosed registers for the fl ash memory in rx111 group user's manual: hardware. table 1.1 added registers for the flash memory product category mpu & mcu document no. tn-rx*-a0 88a/e rev . 1.00 title disclosed regi sters for the flash memory in the rx111 group information category technical notification applicable product rx111 group lot no. reference document rx111 group user's manual: hardware rev.1.00 (r01uh0365ej0100) all no. register name symbol address number of bits 1 flash start-up setting monitor register fscmr 007f c0b0h 16 2 flash access window start address monitor register fawsmr 007f c0b2h 16 3 flash access window end address monitor register fawemr 007f c0b4h 16 4 flash initial setting register fisr 007f c0b6h 8 5 flash extra area control register fexcr 007f c0b7h 8 6 flash error address monitor register l feaml 007f c0b8h 8 7 flash error address monito r register h feamh 007f c0bah 8 8 protection unlock re gister fpr 007f c0c0h 8 9 protection unlock status register fpsr 007f c0c1h 8 10 flash read buffer register l frbl 007f c0c2h 16 11 flash read buffer register h frbh 007f c0c4h 16 12 flash p/e mode control register fpmcr 007f ff80h 8 13 flash area select register fasr 007f ff81h 8 14 flash processing start address register l fsarl 007f ff82h 8 15 flash processing start address register h fsarh 007f ff84h 8 16 flash control register fcr 007f ff85h 8 17 flash processing end address register l fearl 007f ff86h 16 18 flash processing end address register h fearh 007f ff88h 8 19 flash reset register fresetr 007f ff89h 8 20 flash status register 0 fstatr0 007f ff8ah 8 21 flash status register 1 fstatr1 007f ff8bh 8 22 flash write buffer register l fwbl 007f ff8ch 16 23 flash write buffer register h fwbh 007f ff8eh 16 24 flash p/e mode entry register fentryr 007f ffb2h 16
page 2 of 9 renesas technical update tn-rx*-a0 88a/e date: feb . 25 , 2014 bit assignments and descriptions for the regist ers listed in table 1. 1 are added as follows: 1. flash start-up setting monitor register (fscmr) 2. flash access window start address monitor register (fawsmr) 3. flash access window end address monitor register (fawemr) address(es): 007f c0b0h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ???????sasmf???????? value after reset: 0111111 the value set by the user 00000000 bit symbol bit name description r/w b7 to b0 ? reserved these bits are read as 0. r b8 sasmf start-up area setting monitor flag 0: setting to start up using the alternative area 1: setting to start up using the default area r b14 to b9 ? reserved these bits are read as 1. writing to these bits has no effect. r b15 ? reserved this bit is read as 0. writing to this bit has no effect. r address(es): 007f c0b2h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ?????? value after reset: 000000 the value set by the user address(es): 007f c0b4h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ?????? value after reset: 000000 the value set by the user
page 3 of 9 renesas technical update tn-rx*-a0 88a/e date: feb. 25, 2014 4. flash initial setting register (fisr) 5. flash extra area control register (fexcr) 6. flash error address monitor register l (feaml) address(es): 007f c0b6h b7 b6 b5 b4 b3 b2 b1 b0 sas[1:0] ? pcka[4:0] value after reset: 00000000 bit symbol bit name description r/w b4 to b0 pcka[4:0] peripheral clock notification these bi ts are used to set the frequency of the flashif clock (fclk). r/w b5 ? reserved this bit is read as 0. the write value should be 0. r/w b7, b6 sas[1:0] start-up area select b7 b6 0 x: the start-up area is selected according to the start-up area settings of the extra area. 1 0: the start-up area is switched to the default area temporarily. 1 1: the start-up area is switched to the alternate area temporarily. r/w address(es): 007f c0b7h b7 b6 b5 b4 b3 b2 b1 b0 opst???? cmd[2:0] value after reset: 00000000 bit symbol bit name description r/w b2 to b0 cmd[2:0] software command setting b2 b0 0 0 1: start-up area information program 0 1 0: access window information program settings other than above are prohibited. r/w b6 to b3 ? reserved these bits are read as 0. the write value should be 0. r/w b7 opst processing start 0: processing stops. 1: processing starts. r/w address(es): 007f c0b8h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 value after reset: 0000000000000000
page 4 of 9 renesas technical update tn-rx*-a0 88a/e date: feb. 25, 2014 7. flash error address monitor register h (feamh) 8. protection unlock register (fpr) 9. protection unlock status register (fpsr) 10. flash read buffer register l (frbl) 11. flash read buffer register h (frbh) address(es): 007f c0bah b7 b6 b5 b4 b3 b2 b1 b0 ???? value after reset: 00000000 address(es): 007f c0c0h b7 b6 b5 b4 b3 b2 b1 b0 value after reset: xxxxxxxx address(es): 007f c0c1h b7 b6 b5 b4 b3 b2 b1 b0 ??????? perr value after reset: 00000000 bit symbol bit name description r/w b0 perr protect error flag 0: no error 1: an error occurs. r b7 to b1 ? reserved these bits are read as 0. r address(es): 007f c0c2h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 value after reset: 0000000000000000 address(es): 007f c0c4h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 value after reset: 0000000000000000
page 5 of 9 renesas technical update tn-rx*-a0 88a/e date: feb. 25, 2014 12. flash p/e mode control register (fpmcr) 13. flash area select register (fasr) 14. flash processing start address register l (fsarl) address(es): 007f ff80h b7 b6 b5 b4 b3 b2 b1 b0 fms2 lvpe ? fms1 rpdis ? fms0 ? value after reset: 00001000 bit symbol bit name description r/w b0 ? reserved this bit is read as 0. the write value should be 0. r/w b1 fms0 flash operating mode select 0 fms2 fms1 fms0 0 0 0: rom read mode 0 1 1: discharge mode 1 1 1 1: discharge mode 2 1 0 1: rom p/e mode 0 1 0: e2 dataflash p/e mode settings other than above are prohibited. r/w b2 ? reserved this bit is read as 0. the write value should be 0. r/w b3 rpdis rom p/e disable 0: rom programming/erasure enabled 1: rom programming/erasure disabled r/w b4 fms1 flash operating mode select 1 see the fms0 bit. r/w b5 ? reserved this bit is read as 0. the write value should be 0. r/w b6 lvpe low-voltage p/e mode enable 0: low-voltage p/e mode disabled 1: low-voltage p/e mode enabled r/w b7 fms2 flash operating mode select 2 see the fms0 bit. r/w address(es): 007f ff81h b7 b6 b5 b4 b3 b2 b1 b0 ???????exs value after reset: 00000000 bit symbol bit name description r/w b0 exs extra area select 0: user area or data area 1: extra area r/w b7 to b1 ? reserved these bits are read as 0. the write value should be 0. r/w address(es): 007f ff82h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 value after reset: 0000000000000000
page 6 of 9 renesas technical update tn-rx*-a0 88a/e date: feb. 25, 2014 15. flash processing start address register h (fsarh) 16. flash control register (fcr) 17. flash processing end address register l (fearl) 18. flash processing end address register h (fearh) address(es): 007f ff84h b7 b6 b5 b4 b3 b2 b1 b0 ???? value after reset: 00000000 address(es): 007f ff85h b7 b6 b5 b4 b3 b2 b1 b0 opst stop ? drc cmd[3:0] value after reset: 00000000 bit symbol bit name description r/w b3 to b0 cmd[3:0] software command setting b3 b0 0 0 0 1: program 0 0 1 1: block erase 0 1 0 1: consecutive read 1 0 1 1: blank check settings other than above are prohibited. r/w b4 drc data read completion 0: data is not read or next data is requested. 1: data reading is completed. r/w b5 ? reserved this bit is read as 0. the write value should be 0. r/w b6 stop forced processing stop when this bit is set to 1, the processing being executed can be forcibly stopped. r/w b7 opst processing start 0: processing stops. 1: processing starts. r/w address(es): 007f ff86h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 value after reset: 0000000000000000 address(es): 007f ff88h b7 b6 b5 b4 b3 b2 b1 b0 ???? value after reset: 00000000
page 7 of 9 renesas technical update tn-rx*-a0 88a/e date: feb. 25, 2014 19. flash reset register (fresetr) 20. flash status register 0 (fstatr0) address(es): 007f ff89h b7 b6 b5 b4 b3 b2 b1 b0 ??????? frese t value after reset: 00000000 bit symbol bit name description r/w b0 freset flash reset 0: flash control circuit reset is released. 1: flash control circuit is reset. r/w b7 to b1 ? reserved these bits are read as 0. the write value should be 0. r/w address(es): 007f ff8ah b7 b6 b5 b4 b3 b2 b1 b0 ?? eilgle rr ilgler r bcerr ? prger r ererr value after reset: x0000000 bit symbol bit name description r/w b0 ererr erase error flag 0: erasure terminates normally. 1: an error occurs during erasure. r b1 prgerr program error flag 0: programming terminates normally. 1: an error occurs during programming. r b2 ? reserved this bit is read as 0. r b3 bcerr blank check error flag 0: bl ank checking terminates normally. 1: an error occurs during blank checking. r b4 ilglerr illegal command error flag 0: no illegal software command or illegal access is detected. 1: an illegal command or illegal access is detected. r b5 eilglerr extra area illegal command error flag 0: no illegal command or illegal access to the extra area is detected. 1: an illegal command or illegal access to the extra area is detected. r b7, b6 ? reserved these bits are read as 0. r
page 8 of 9 renesas technical update tn-rx*-a0 88a/e date: feb. 25, 2014 21. flash status register 1 (fstatr1) 22. flash write buffer register l (fwbl) 23. flash write buffer register h (fwbh) address(es): 007f ff8bh b7 b6 b5 b4 b3 b2 b1 b0 exrdy frdy ? ? ? ? drrdy ? value after reset: 00000100 bit symbol bit name description r/w b0 ? reserved this bit is read as 0. r b1 drrdy data read ready flag 0: no valid data in frbh and frbl registers 1: valid data in frbh and frbl registers r b2 ? reserved this bit is read as 1. r b5 to b3 ? reserved these bits are read as 0. r b6 frdy flash ready flag 0: other than below 1: 00h can be written to the fcr register (processing to complete the software command). r b7 exrdy extra area ready flag 0: other than below 1: 00h can be written to the fexcr register (processing to complete the software command). r address(es): 007f ff8ch b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 value after reset: 0000000000000000 address(es): 007f ff8eh b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 value after reset: 0000000000000000
page 9 of 9 renesas technical update tn-rx*-a0 88a/e date: feb. 25, 2014 24. flash p/e mode entry register (fentryr) address(es): 007f ffb2h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 fekey[7:0] fentr yd ?????? fentr y0 value after reset: 0000000000000000 bit symbol bit name description r/w b0 fentry0 rom p/e mode entry 0 0: rom is in read mode. 1: rom can be placed in p/e mode. r/w b6 to b1 ? reserved these bits are read as 0. the write value should be 0. r/w b7 fentryd e2 dataflash p/e mode entry 0: e2 dataflash is in read mode. 1: e2 dataflash can be placed in p/e mode. r/w b15 to b8 fekey[7:0] key code the fekey[7:0] bits are used to control rewiring of the fentryr register. when rewriting the value of the lower-order 8 bits, set the fekey[7:0] bits to aah at the same time (write this register in 16 bits). the fekey[7:0] bits are read as 00h. r/w
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